flopz.arch.riscv.rv32i package
Submodules
flopz.arch.riscv.rv32i.instructions module
- class R32iADD(rd, rs1, rs2)
- class R32iADDI(rd, rs, imm)
- class R32iAND(rd, rs1, rs2)
- class R32iANDI(rd, rs, imm)
- class R32iAUIPC(rd, imm)
- class R32iBEQ(rs1, rs2, imm)
- class R32iBGE(rs1, rs2, imm)
- class R32iBGEU(rs1, rs2, imm)
- class R32iBLT(rs1, rs2, imm)
- class R32iBLTU(rs1, rs2, imm)
- class R32iBNE(rs1, rs2, imm)
- class R32iCSRRC(rd, csr, rs)
- class R32iCSRRCI(rd, csr, imm)
- class R32iCSRRS(rd, csr, rs)
- class R32iCSRRSI(rd, csr, imm)
- class R32iCSRRW(rd, csr, rs)
- class R32iCSRRWI(rd, csr, imm)
- class R32iEBREAK
- class R32iECALL
- class R32iFENCE(pi, po, pr, pw, si, so, sr, sw)
- class R32iFENCEI
- class R32iJAL(rd, imm)
- class R32iJALR(rd, rs, imm)
- class R32iLB(rd, rs, imm)
- class R32iLBU(rd, rs, imm)
- class R32iLH(rd, rs, imm)
- class R32iLHU(rd, rs, imm)
- class R32iLUI(rd, imm)
- class R32iLW(rd, rs, imm)
- class R32iOR(rd, rs1, rs2)
- class R32iORI(rd, rs, imm)
- class R32iSB(rs, imm, ra)
- class R32iSH(rs, imm, ra)
- class R32iSLL(rd, rs1, rs2)
- class R32iSLLI(rd, rs, imm)
- class R32iSLTI(rd, rs, imm)
- class R32iSLTIU(rd, rs, imm)
- class R32iSLTU(rd, rs1, rs2)
- class R32iSRA(rd, rs1, rs2)
- class R32iSRAI(rd, rs, imm)
- class R32iSRL(rd, rs1, rs2)
- class R32iSRLI(rd, rs, imm)
- class R32iSUB(rd, rs1, rs2)
- class R32iSW(rs, imm, ra)
- class R32iXOR(rd, rs1, rs2)
- class R32iXORI(rd, rs, imm)
- class RiscvBForm
Bases:
flopz.arch.riscv.rv32i.instructions.RiscvInstructionForm- parse(instruction)
- Parameters
instruction (
Instruction) –
- class RiscvIForm
Bases:
flopz.arch.riscv.rv32i.instructions.RiscvInstructionForm- parse(instruction)
- Parameters
instruction (
Instruction) –
- class RiscvInstruction(form, addr=0, bit_length=32, **kwargs)
Bases:
flopz.arch.instruction.InstructionBase class for all RiscV instructions.
Will parse the given InstructionForm instance to add the operands to the instruction and then use the keyword arguments to set the different operands.
- Parameters
form (
RiscvInstructionForm) –addr (
int) –bit_length (
int) –
- class RiscvInstructionForm
Bases:
objectBase class for the different forms a riscv instruction can have. Forms add the operands to the instruction object with their parse function.
- parse(instruction)
- Parameters
instruction (
Instruction) –
- class RiscvJForm
Bases:
flopz.arch.riscv.rv32i.instructions.RiscvInstructionForm- parse(instruction)
- Parameters
instruction (
Instruction) –
- class RiscvRForm
Bases:
flopz.arch.riscv.rv32i.instructions.RiscvInstructionForm- parse(instruction)
- Parameters
instruction (
Instruction) –
- class RiscvSForm
Bases:
flopz.arch.riscv.rv32i.instructions.RiscvInstructionForm- parse(instruction)
- Parameters
instruction (
Instruction) –
- class RiscvUForm
Bases:
flopz.arch.riscv.rv32i.instructions.RiscvInstructionForm- parse(instruction)
- Parameters
instruction (
Instruction) –
- class SLT(rd, rs1, rs2)
flopz.arch.riscv.rv32i.rv32i_arch module
- class RV32IArch
Bases:
flopz.arch.riscv.riscv_generic_arch.RiscvGenericArchitecture