flopz.arch.riscv.rv32c package

Submodules

flopz.arch.riscv.rv32c.instructions module

class CADD(rd, rs2): Bases: flopz.arch.riscv.rv32i.instructions.RiscvInstruction

class CADDI(rd, imm)

Bases: flopz.arch.riscv.rv32i.instructions.RiscvInstruction

Parameters: imm (int) –

class CADDI16SP(imm)

Bases: flopz.arch.riscv.rv32i.instructions.RiscvInstruction

Parameters: imm (int) –

class CADDI4SPN(rd, imm)

Bases: flopz.arch.riscv.rv32i.instructions.RiscvInstruction

Parameters: imm (int) –

class CAND(rd, rs2): Bases: flopz.arch.riscv.rv32i.instructions.RiscvInstruction

class CANDI(rd, imm): Bases: flopz.arch.riscv.rv32i.instructions.RiscvInstruction

class CBEQZ(rs1, offset)

Bases: flopz.arch.riscv.rv32i.instructions.RiscvInstruction

Parameters: offset (int) –

class CBNEZ(rs1, offset)

Bases: flopz.arch.riscv.rv32i.instructions.RiscvInstruction

Parameters: offset (int) –

class CEBREAK: Bases: flopz.arch.riscv.rv32i.instructions.RiscvInstruction

class CJ(offset): Bases: flopz.arch.riscv.rv32i.instructions.RiscvInstruction

class CJAL(offset): Bases: flopz.arch.riscv.rv32i.instructions.RiscvInstruction

class CJALR(rs1): Bases: flopz.arch.riscv.rv32i.instructions.RiscvInstruction

class CJR(rs1): Bases: flopz.arch.riscv.rv32i.instructions.RiscvInstruction

class CLI(rd, imm)

Bases: flopz.arch.riscv.rv32i.instructions.RiscvInstruction

Parameters: imm (int) –

class CLUI(rd, imm)

Bases: flopz.arch.riscv.rv32i.instructions.RiscvInstruction

Parameters: imm (int) –

class CLW(dest, base, offset)

Bases: flopz.arch.riscv.rv32i.instructions.RiscvInstruction

Parameters: offset (int) –

class CLWSP(rd, offset)

Bases: flopz.arch.riscv.rv32i.instructions.RiscvInstruction

Parameters: offset (int) –

class CMV(rd, rs2): Bases: flopz.arch.riscv.rv32i.instructions.RiscvInstruction

class CNOP: Bases: flopz.arch.riscv.rv32i.instructions.RiscvInstruction

class COR(rd, rs2): Bases: flopz.arch.riscv.rv32i.instructions.RiscvInstruction

class CSLLI(rd, shift): Bases: flopz.arch.riscv.rv32i.instructions.RiscvInstruction

class CSRAI(rd, shift): Bases: flopz.arch.riscv.rv32i.instructions.RiscvInstruction

class CSRLI(rd, shift): Bases: flopz.arch.riscv.rv32i.instructions.RiscvInstruction

class CSUB(rd, rs2): Bases: flopz.arch.riscv.rv32i.instructions.RiscvInstruction

class CSW(src, base, offset)

Bases: flopz.arch.riscv.rv32i.instructions.RiscvInstruction

Parameters: offset (int) –

class CSWSP(rs2, offset)

Bases: flopz.arch.riscv.rv32i.instructions.RiscvInstruction

Parameters: offset (int) –

class CXOR(rd, rs2): Bases: flopz.arch.riscv.rv32i.instructions.RiscvInstruction

class RiscvCAForm

Bases: flopz.arch.riscv.rv32c.instructions.RiscvCompactInstructionForm

parse(instruction)

Parameters: instruction (Instruction) –

class RiscvCBForm

Bases: flopz.arch.riscv.rv32c.instructions.RiscvCompactInstructionForm

parse(instruction)

Parameters: instruction (Instruction) –

class RiscvCIForm

Bases: flopz.arch.riscv.rv32c.instructions.RiscvCompactInstructionForm

parse(instruction)

Parameters: instruction (Instruction) –

class RiscvCIWForm

Bases: flopz.arch.riscv.rv32c.instructions.RiscvCompactInstructionForm

parse(instruction)

Parameters: instruction (Instruction) –

class RiscvCJForm

Bases: flopz.arch.riscv.rv32c.instructions.RiscvCompactInstructionForm

parse(instruction)

Parameters: instruction (Instruction) –

class RiscvCLForm

Bases: flopz.arch.riscv.rv32c.instructions.RiscvCompactInstructionForm

parse(instruction)

Parameters: instruction (Instruction) –

class RiscvCRForm

Bases: flopz.arch.riscv.rv32c.instructions.RiscvCompactInstructionForm

parse(instruction)

Parameters: instruction (Instruction) –

class RiscvCSForm

Bases: flopz.arch.riscv.rv32c.instructions.RiscvCompactInstructionForm

parse(instruction)

Parameters: instruction (Instruction) –

class RiscvCSSForm

Bases: flopz.arch.riscv.rv32c.instructions.RiscvCompactInstructionForm

parse(instruction)

Parameters: instruction (Instruction) –

class RiscvCompactInstructionForm

Bases: flopz.arch.riscv.rv32i.instructions.RiscvInstructionForm

Compact instruction form base class.

parse(instruction)

Parameters: instruction (Instruction) –

get_compact_register_encoding(reg)

Returns the compact encoding for r8-r16.

Parameters: reg (Union[int, RiscvRegister]) –

flopz.arch.riscv.rv32c package

Submodules

flopz.arch.riscv.rv32c.instructions module

Module contents